Google adds TPU 8tx for secure inference, TPU 8i Max for long context

Google announced two more eighth-generation TPU systems on 9 November 2026: TPU 8tx, for confidential, secure inference; and TPU 8i Max, aimed at very large context windows and, Google says, its highest per-rack compute density.

Google says the pair joins TPU 8t, for training, and TPU 8i, for real-time reasoning, which it introduced in April at Google Cloud Next, and that it has never before launched four TPU systems within one year. It says the new systems answer requests from outside organisations: businesses wanting accelerators that can work across huge model contexts, and highly regulated customers wanting specialised encryption.

Google says TPU 8tx is built on TPU 8t's chip design and runs with AMD's 5th Generation EPYC host processors. Google notes that data is usually encrypted in storage and in transit but must be decrypted in memory to be processed; it says TPU 8tx builds protection into the hardware, so confidential data and model weights stay isolated even during use. The system also uses the low-latency Boardfly network Google created for real-time reasoning, and Google claims latency up to two times lower than TPU 8t, at a near-zero performance penalty. Google aims it at governments and regulated enterprises, and says it can also handle small-scale training, so teams can fine-tune, distil and reinforcement-train models on one system without moving private data between clusters.

For TPU 8i Max, Google says it placed two TPU 8i chips on a single package. That gives twice TPU 8i's compute, SRAM and HBM bandwidth, which Google says addresses the memory bottleneck met when dozens of agents work at once across a whole codebase or long stretches of video. Because the system carries twice the silicon in the current rack footprint, Google says data centres can deploy considerably more compute for each square foot and each watt.

Google also says it is releasing TPU Sync as open-source software. It describes TPU Sync as a model-state layer that joins the data centre network, shared storage, host DRAM and chip HBM into one memory hierarchy, and says it cuts time to first token and KV transfer latency by more than 90 percent.